Designing the right printed circuit board stackup can make or break your product performance. If the product has circuitry that is impedance and transmission loss sensitive, then paying attention to conductor surface roughness is paramount. But sometimes the roughness of adjacent reference plane(s) is overlooked. If the adjacent high-speed signal layer is using smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly cause your product to fail compliance. So how do we know this before finalizing the stackup? Since we do not have any empirical data to go by, we rely on heuristic modeling methods that rely solely on published parameters found in manufacturer’s data sheets.