The increasing complexity in today’s IC packages and PCBs can have a huge impact on the performance and functionality of the IC. In addition, higher densities, lower power, and tighter cost margins with a shorter time to market all need to be taken into account when designing an IC along with its package and maybe even the PCB. It’s no wonder that chip/package/PCB co-design and co-analysis has now become the norm. However, there hasn’t been an automated or efficient process for designing concurrently across all three domains. What designers need is a formal and automated co-design flow to help minimize the potential for human error. This paper outlines a new methodology that provides such a solution.