What are buried capacitances? How do they improve PCBs?
Editorial Team - PCB Directory
Feb 28, 2025
A Buried Capacitance PCB, also known as embedded capacitance or power-ground laminate technology, is a PCB that integrates capacitance directly into the board structure. This is achieved by creating an extremely thin dielectric layer between power and ground planes within the PCB stack-up. By reducing the dielectric thickness and using materials with high dielectric constants, significant capacitance is embedded within the board, eliminating the need for discrete decoupling capacitors. This technology improves power integrity, enhances signal integrity, reduces EMI, and enables efficient PCB space utilization.
Structure of Buried Capacitance PCBs
In a buried capacitance PCB, the integrated ultra-thin dielectric layer has a thickness of less than 10 μm between the power and ground planes. This reduces the distance between these planes, which shortens current paths and lowers parasitic effects. The distributed capacitance improves high-frequency performance due to the effective suppression of noise on the PCB and enhances the power integrity in the PCB as well. Additionally, due to the power distribution network impedance being reduced considerably, these boards have higher signal stability.
Material selection is important to implement effective buried capacitance. Materials with high dielectric constants are selected to increase the capacitance and ultra-thin copper foils are used to further reduce the distance between power and ground planes. The prepreg and core materials are selected accordingly so that they can work optimally with the very thin dielectric and copper layers to ensure overall PCB reliability.
PCB with an embedded (buried) capacitor
A well-designed PCB stack-up is crucial to optimize buried capacitance. The buried capacitance layers are usually located near the center of the stack-up for maximum performance. Proper signal layer distribution around the capacitance structure helps maintain signal integrity, while careful impedance control—achieved by adjusting trace widths and spacings—ensures consistent electrical performance. The optimization of the power plane layout improves the benefits of buried capacitance. The proper partitioning of different voltage domains helps in maintaining capacitive coupling while minimal voids in the power plane ensure uniform capacitance across the PCB. In addition, the thickness of the copper used should be sufficient to support the required current capacity without excessive resistance.
Advanced simulation and modeling tools have improved the designs of buried capacitance PCBs. 3D electromagnetic simulation models showcase the complex structure of the PCB accurately, and power integrity analysis of these digital models proves the Power Distribution Network (PDN) performance, which is calculated by measuring the DC resistivity, capacitor loop inductance, and target impedance decoupling of a PCB for the detection of possible weaknesses. Simulations for signal integrity ensure that high-speed signals do not degrade and are stable, thus reducing the risk of signal degradation.
Advantages:
Challenges and Limitations
The production of buried capacitance PCBs is challenging due to the utilization of ultra-thin materials. The handling of these materials is sensitive and necessitates special equipment to avoid damage. Moreover, the layer registration must be highly accurate to achieve uniform capacitance. The manufacturing process complexity can also lead to lower yields, especially in the early stages of its adoption.
Although buried capacitance may save costs in the long run, the upfront investment can be high. Specialized dielectric materials drive up material costs, and a complex manufacturing process, as well as possible yield losses, contribute to higher production costs. Additionally, designing PCBs with buried capacitance requires more time and expertise, thereby driving up design costs.
Few commercial PCB design packages support buried capacitance as their native or out-of-the-box implementation. Designing ultra-thin dielectric layers and generally modeling distributed capacitance with tolerable accuracy represent significant difficulties when using available toolsets.
Buried capacitance can not be considered a universal solution for signal integrity problems. The technology has frequency limitations because there is an upper limit beyond which its effectiveness diminishes. The achievable capacitance per unit area may also be lower compared to certain discrete components. Thin dielectric layers also impose voltage constraints on the PCB, limiting the maximum operating voltage.
Applications
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